Jose Nunez-Yanez
Professor
Publikationslista
Tidskriftsartiklar
2024
Habib Taha Kose, Jose Nunez-Yanez, Robert Piechocki, James Pope, 
A Survey of Computationally Efficient Graph Neural Networks for Reconfigurable Systems, Information 15:377 (2024) 
https://doi.org/10.3390/info15070377
Zichao Shen, Jose Luis Nunez-Yanez, Naim Dahnoun, Advanced Millimeter-Wave Radar System for Real-Time Multiple-Human Tracking and Fall Detection, Sensors 24:3660 (2024) https://doi.org/10.3390/s24113660
2023
Jose Nunez-Yanez, Andres Otero, Eduardo de la Torre, Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite, Microprocessors and microsystems 98:104801 (2023) https://doi.org/10.1016/j.micpro.2023.104801
2022
J. Nunez-Yanez, Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite, IEEE Micro, 1-10 (2022) https://doi.org/10.1109/MM.2022.3196705
Jose Luis Nunez-Yanez, Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite, IEEE Micro 42:55-66 (2022) https://doi.org/10.1109/MM.2022.3196705
Andrés Rodríguez, Angeles G. Navarro, Kris Nikov, José L. Núñez-Yáñez, Ruben Gran, Darío Suárez Gracia, Rafael Asenjo, Lightweight asynchronous scheduling in heterogeneous reconfigurable systems. J. Syst. Archit. 124:102398 (2022) https://doi.org/10.1016/j.sysarc.2022.102398
Kris Nikov, Marcos Martínez, Simon Wegener, Jose Nunez-Yanez, Zbigniew Chamski, Kyriakos Georgiou, Kerstin Eder, “Robust and Accurate Fine-Grain Power Models for Embedded Systems With No On-Chip PMU,” in IEEE Embedded Systems Letters, 14:147-150 (2022) https://do.org/10.1109/LES.2022.3147308
Z. Shen, N. Howard, J. Nunez-Yanez, Big–Little Adaptive Neural Networks on Low-Power Near-Subthreshold Processors. J. Low Power Electron. Appl. 12:28 (2022) https://doi.org/10.3390/jlpea12020028
2021
Jose Nunez-Yanez, Mohammad Hosseinabady, Sparse and dense matrix multiplication hardware for heterogeneous multi-precision neural networks, Array 12:100101 (2021) https://doi.org/10.1016/j.array.2021.100101
Jose Nunez-Yanez, Neil Howard, Energy-efficient neural networks with near-threshold processors and hardware accelerators, J. Syst. Arch. 116:102062 (2021) https://doi.org/10.1016/j.sysarc.2021.102062
2020
E. Y. L. Kwan, J. Nunez-Yanez, Entropy-Driven Adaptive Filtering for High-Accuracy and Resource-Efficient FPGA-Based Neural Network Systems, Electronics 9:1765 (2020) https://doi.org/10.3390/electronics9111765
M. Hosseinabady and J. L. Nunez-Yanez, A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication using High-Level Synthesis, IEEE Trans Computer-Aided Design of Integrated Circuits and Systems 39:1272-1285 (2020) https://doi.org/10.1109/TCAD.2019.2912923
Yang Zhang, Paul Hutchinson, Nicholas A. J. Lieven, Jose Nunez-Yanez, Remaining Useful Life Estimation Using Long Short-Term Memory Neural Networks and Deep Fusion, IEEE Access 8:19033-19045, (2020) https://doi.org/10.1109/ACCESS.2020.2966827
2019
J. Nunez-Yanez, Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling, in IEEE Transactions on Computers 68:676-687 (2019) https://doi.org/10.1109/TC.2018.2879333
J. Nunez-Yanez, S. Amiri, M. Hosseinabady, A. Rodríguez, R. Asenjo, A. Navarro, D. Suarez, R. Gran, Simultaneous multiprocessing in a software-defined heterogeneous FPGA, J. Supercomput. 75:4078-4095 (2019) https://doi.org/10.1007/s11227-018-2367-9
A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs J. Syst. Arch. 98:27-40 (2019) https://doi.org/10.1016/j.sysarc.2019.06.006
A. Rodríguez, A. Navarro, R. Asenjo, F. Corbera, R. Gran, D. Suárez, J. Nunez-Yanez, Parallel Multiprocessing and Scheduling on the Heterogeneous Xeon+FPGA Platform. Journal of Supercomputing 76:4645-4665 (2019) https://doi.org/10.1007/s11227-019-02935-1
Yang Zhang, Paul Hutchinson, Nicholas A.J. Lieven, Jose Nunez-Yanez, Adaptive event-triggered anomaly detection in compressed vibration data, Mechanical Systems and Signal Processing 122:480-501 (2019) https://doi.org/10.1016/j.ymssp.2018.12.039
2018
M. A. Bin Zainol, J. Nunez-Yanez, Extending the PCIe Interface with Parallel Compression/Decompression Hardware for Energy and Performance Optimization, International Journal on Future Revolution in Computer Science and Communication Engineering (IJFRSCE) 4(2):405-419 (2018) https://www.ijfrcsce.org/index.php/ijfrcsce/article/view/1233
Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Dynamic Energy Management of FPGA Accelerators in Embedded Systems, ACM Trans. Embed. Comput. Syst. 17:63, pp 1-26 (2018) https://doi.org/10.1145/3182172
Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, and Georgios Zervas, Reconfigurable Network Stream Processing on Virtualized FPGA Resources, International Journal of Reconfigurable Computing 2018:8785903 (2018) https://doi.org/10.1155/2018/8785903
Qianqiao Chen, Vaibhawa Mishra, Jose Nunez-Yanez, and Georgios Zervas, Reconfigurable Network Stream Processing on Virtualized FPGA Resources, International Journal of Reconfigurable Computing, 2018:8785903, pp1-11 (2018) https://doi.org/10.1155/2018/8785903
2017
Jose Nunez-Yanez, Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors, Microprocessors and Microsystems 51:227-238 (2017) https://doi.org/10.1016/j.micpro.2017.04.021
Felipe Galindo Sanchez, Jose Nunez-Yanez, Energy proportional streaming spiking neural network in a reconfigurable system, Microprocessors and Microsystems, 53:57-67 (2017) https://doi.org/10.1016/j.micpro.2017.06.018
2016
J. Nunez-Yanez, M. Hosseinabady, A. Beldachi, Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling, IEEE Transactions on Computers, 65:1484-1493 (2016) https://doi.org/10.1109/TC.2015.2435771
2015
J. Nunez-Yanez, Adaptive Voltage Scaling with in-situ Detectors in Commercial FPGAs, IEEE Transactions on Computers 99:1 (2015) https://doi.org/10.1109/TC.2013.73
J. C. M. Eugenio, J. P. McGeehan, J. L. Nunez-Yanez, Biologically compatible neural networks with reconfigurable hardware, Microprocessors and Microsystems, 39:693-703 (2015) https://doi.org/10.1016/j.micpro.2015.09.003
2014
J. L. Nunez-Yanez, Geza Lore, Enabling accurate modeling of power and energy consumption in an ARM-based System-on-chip, Microprocessors and Microsystems 37:319-332 (2014) https://doi.org/10.1016/j.micpro.2012.12.004
Arash Farhadi Beldachi, Jose L. Nunez-Yanez, Run-time power and performance scaling in 28 nm FPGAs, IET Computers & Digital Techniques 8:178-186 (2014) https://doi.org/10.1049/iet-cdt.2013.0117
Arash Farhadi Beldachi, Simon Hollis, Jose L. Nunez-Yanez, eXtended Torus routing algorithm for networks-on-chip, a routing algorithm for dynamically reconfigurable networks-on-chip, IET Computers & Digital Techniques 8:148-162 (2014) https://doi.org/10.1049/iet-cdt.2013.0087
J. Chen, J. L. Nunez-Yanez, A. Achim, Bayesian Video Super-Resolution With Heavy-Tailed Prior Models, IEEE Transactions on Circuits and Systems for Video Technology 24:905-914 (2014) https://doi.org/10.1109/TCSVT.2014.2302549
2013
A. F. Beldachi, M. Hosseinabady, J. Nunez-Yanez, Configurable Router Design for Dynamically Reconfigurable Systems based on the SoCWire NoC, International Journal of Reconfigurable and Embedded Systems (IJRES) 2:1 (2013) https://iaesjournal.com/online/index.php/IJRES/article/view/2144
Y. Zhang, J. Mcgeehan, E. Regan, S. Kelly, J. Nunez-Yanez, Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic, IEEE Transactions on Computers 62:599-608 (2013) https://doi.org/10.1109/TC.2011.257
2012
J. L. Nunez-Yanez, A. Nabina, E. Hung, G. Vafiadis, Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20:437-448 (2012) https://doi.org/10.1109/TVLSI.2010.2104166
Atukem Nabina, Jose Luis Nunez-Yanez, Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform, ACM Trans. Reconfigurable Technol. Syst. 5:20, pp 1-22 (2012) https://doi.org/10.1145/2392616.2392618
J. Chen, J. Nunez-Yanez, A. Achim, Video Super-resolution Using Generalized Gaussian Markov Random Fields, IEEE Signal Processing Letters 19:63-66 (2012) https://doi.org/10.1109/LSP.2011.2178595
Jin Chen, J. Nunez-Yanez, A. Achim, Video Super-Resolution Using Generalized Gaussian Markov Random Fields, IEEE Signal Processing Letters 19:63-66 (2012) https://doi.org/10.1109/LSP.2011.2178595
M. Hosseinabady, J. L. Nunez-Yanez, Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation, IET Computers & Digital Techniques 6:384-395 (2012) https://doi.org/10.1049/iet-cdt.2012.0001
M. Hosseinabady, J. L. Nunez-Yanez, Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles, IET Computers & Digital Techniques 6:1-11 (2012) https://doi.org/10.1049/iet-cdt.2010.0097
T. Spiteri, J. Núñez-Yáñez, Scalable video coding with multi-layer motion vector palettes, IET Image Processing 6:1319-1330 (2012) https://doi.org/10.1049/iet-ipr.2012.0048
Xiaolin Chen, Nishan Canagarajah, Jose L. Nunez-Yanez, Raffaele Vitulli, Lossless video compression based on backward adaptive pixel-based fast motion estimation, Signal Processing: Image Communication 27:961-972 (2012) https://doi.org/10.1016/j.image.2012.06.004
2011
Jose L. Nunez-Yanez, T. Spiteri, G. Vafiadis, Multi-standard reconfigurable motion estimation processor for hybrid video codecs, IET Computers & Digital Techniques 5:73-85 (2011) https://doi.org/10.1049/iet-cdt.2009.0070
2010
Edward M Regan, James B Uney, Andrew D Dick, Yiwei Zhang, Jose Nunez-Yanez, Joseph P McGeehan, Frederik Claeyssens, Stephen Kelly, Differential patterning of neuron, glial and neural progenitor cells on phosphorus-doped and UV irradiated diamond-like carbon, Biomaterials 31:207-215 (2010) https://doi.org/10.1016/j.biomaterials.2009.09.042
2009
Xiaolin Chen, Nishan Canagarajah, Jose Nunez-Yanez, Backward Adaptive Pixel-Based Fast Predictive Motion Estimation, IEEE Signal Processing Letters 16:370-373 (2009) https://doi.org/10.1016/j.image.2012.06.004
2008
J. L. Nunez-Yanez, D. Edwards, A. M. Coppola, Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems, IET Computers & Digital Techniques 2:184-198 (2008) :20060175 https://doi.org/10.1049/iet-cdt
V. A. Chouliaras, V. M. Dwyer, S. Agha, J. L. Nunez-Yanez, D. Reisis, Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study, Integration, the VLSI Journal archive 41:135-152 (2008) https://doi.org/10.1016/j.vlsi.2007.02.003
Xiaofeng Wu, V. A. Chouliaras, J. L. Nunez-Yanez, R. M. Goodall, A Novel DeltaSigma Control System Processor and Its VLSI Implementation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16:217-228 (2008) https://doi.org/10.1109/TVLSI.2007.915396
2007
V. A. Chouliaras, J. L. Nunez-Yanez, Thread Parallel MPEG-2 and MPEG-4 encoders for shared-memory SoC Multiprocessors, International Journal of Computers and Applications, Issue 4 (2007) https://doi.org/10.2316/Journal.202.2007.4.202-2017
2006
J. L. Nunez-Yanez, V. A. Chouliaras, D. Alfonso, F. Rovati, Hardware Assisted Rate Distortion Optimization with Embedded CABAC Accelerator for the H.264 Advanced Video Codec, IEEE Transactions on Consumer Electronics 52:590-598 (2006) https://doi.org/10.1109/TCE.2006.1649684
J. L. Nunez-Yanez, V. A. Chouliaras, Gigabyte per Second Streaming Lossless Data Compression Hardware Based on a Configurable Variable-Geometry CAM Dictionary, IEE Proceedings - Computers and Digital Techniques 153:47-58 (2006) :20045130 https://doi.org/10.1049/ip-cdt
2005
J. L. Nunez-Yanez, V. A. Chouliaras, A Configurable Statistical Lossless Compression Core Based on Variable Order Modelling and Arithmetic Coding, IEEE Transactions on Computers 54:1345-1359 (2005) https://doi.org/10.1109/TC.2005.171
J. L. Nunez-Yanez, V. A. Chouliaras, High-Performance Arithmetic Coding VLSI Macro for the H264 Video Compression Standard, IEEE Transactions on Consumer Electronics 51:144-151 (2005) https://doi.org/10.1109/TCE.2005.1405712
V. A. Chouliaras, J. L. Nunez-Yanez, F. Rovati, D. Alfonso, A Multi-standard Video Coding Accelerator Based on a Vector Architecture, IEEE Transactions on Consumer Electronics 51:160-167 (2005) https://doi.org/10.1109/TCE.2005.1405714
2004
M. Milward, J. L. Nunez-Yanez, D. Mulvaney, Design and Implementation of a Lossless Parallel High-Speed Data Compression System, IEEE Transactions on Parallel and Distributed Systems 15:481-490 (2004) https://doi.org/10.1109/TPDS.2004.7
V. A. Chouliaras, J. L. Nunez-Yanez, K. Koutsomyti, S. R. Parr, D. J. Mulvaney, S. Datta, Development of custom vector accelerator for high-performance speech coding, IEE Electronic Letters, 40:1559-1561 (2004) :20046094 https://doi.org/10.1049/el
2003
J. L. Nunez-Yanez, S. Jones, Gbit/Second Lossless Data Compression Hardware, IEEE Transactions on VLSI Systems (TVLSI) 11:499-510 (2003) https://doi.org/10.1109/TVLSI.2003.812288
J. L. Nunez-Yanez, S. Jones, Run-Length Coding Extensions for High Performance Hardware Data Compression, IEE Proceedings Computers & Digital Techniques 150:387-395 (2003) :20030750 https://doi.org/10.1049/ip-cdt
V. A. Chouliaras, J. L. Nunez-Yanez, Scalar Coprocessors for accelerating the G723.1 and G729A Speech Coders, IEEE Transactions on Consumer Electronics 49:703-710 (2003) https://doi.org/10.1109/TCE.2003.1233807
Konferensartiklar
2024
Mahdieh Grailootanha, Tooraj Nikoubin, Oscar Gustafsson, Jose Luis Nunez-Yanez, Activation Function Integration for Accelerating Multi-Layer Graph Convolutional Neural Networks, 17TH IEEE DALLAS CIRCUITS AND SYSTEMS CONFERENCE, DCAS 2024, Proceedings of the IEEE Dallas Circuits and Systems Workshop, IEEE (2024) https://doi.org/10.1109/DCAS61159.2024.10539892
Olle Hansson, Mahdieh Grailootanha, Oscar Gustafsson, Jose Luis Nunez-Yanez, Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training, APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024, Lecture Notes in Computer Science, pp. 33-47, SPRINGER INTERNATIONAL PUBLISHING AG (2024) https://doi.org/10.1007/978-3-031-55673-9_3
Zichao Shen, Jose Nunez-Yanez, Naim Dahnoun, MMIDNet: Secure Human Identification Using Millimeter-wave Radar and Deep Learning, 2024 13TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING, MECO 2024, Mediterranean Conference on Embedded Computing, pp. 328-334, IEEE (2024) https://doi.org/10.1109/MECO62516.2024.10577920
2023
Jose Nunez-Yanez, Accelerating Graph Neural Networks in Pytorch With HLS and Deep Dataflows, Applied Reconfigurable Computing. Architectures, Tools, and Applications., Francesca Palumbo, Georgios Keramidas, Nikolaos Voros, Pedro C. Diniz (eds.), Lecture Notes in Computer Science, pp. 131-145, Springer, Cham (2023) https://doi.org/10.1007/978-3-031-42921-7_9
Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, Jose Luis Nunez-Yanez, Evolutionary FPGA-based Spiking NeuralNetworks for Continual Learning, APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2023, Lecture Notes in Computer Science, pp. 260-274, Springer Nature, Cham (2023) https://doi.org/10.1007/978-3-031-42921-7_18
Simon Wegener, Kris Nikov, Jose Luis Nunez-Yanez, Kerstin Eder, EnergyAnalyzer: Using Static WCET Analysis Techniques to Estimate the Energy Consumption of Embedded Applications, (2023) https://doi.org/10.4230/OASIcs.WCET.2023.9
Zichao Shen, Jose Luis Nunez-Yanez, Naim Danohum, “Multiple Human Tracking and Fall Detection Real-Time System Using Millimeter-Wave Radar and Data Fusion,”, (2023) https://doi.org/10.1109/MECO58584.2023.10155097
2022
Kaan Olgu, Kris Nikov, Jose Luis Nunez-Yanez, Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications, 2022 25th Euromicro Conference on Digital System Design (DSD), EUROMICRO Conference Proceedings, pp. 16-23, Institute of Electrical and Electronics Engineers (IEEE) (2022) https://doi.org/10.1109/DSD57027.2022.00012
Kris Nikov, Kyriakos Georgiou, Zbigniew Chamski, Kerstin Eder, Jose Luis Nunez-Yanez, Accurate Energy Modelling on the Cortex-M0 Processor for Profiling and Static Analysis, 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4, Institute of Electrical and Electronics Engineers (IEEE) (2022) https://doi.org/10.1109/ICECS202256217.2022.9971086
Minxuan Kong, Jose Luis Nunez-Yanez, Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network, Applied Reconfigurable Computing. Architectures, Tools, and Applications, Gan, Lin; Wang, Yu; Xue, Wei; Chau, Thomas (eds.), Lecture Notes in Computer Science, pp. 72-86, Springer Nature (2022) https://doi.org/10.1007/978-3-031-19983-7_6
Minxuan Kong, Kris Nikov, Jose Luis Nunez-Yanez, Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks, 2022 25th Euromicro Conference on Digital System Design (DSD), pp. 01-08, Institute of Electrical and Electronics Engineers (IEEE) (2022) https://doi.org/10.1109/DSD57027.2022.00035
Tommaso Cappello, Gautam Jindal, Jose Nunez-Yanez, Kevin Morris, Power Consumption and Linearization Performance of a Bit- and Frequency-Scalable AM/AM AM/PM Pre-Distortion on FPGA, 2022 International Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits (INMMiC), 07-08 April (2022) https://doi.org/10.1109/INMMiC54248.2022.9762118
Zijie Wang, Jiajun Lu, Jose Luis Nunez-Yanez, A Low-complexity FPGA TDC based on a DSP Delay Line and a Wave Union Launcher, 2022 25th Euromicro Conference on Digital System Design (DSD), EUROMICRO Conference Proceedings, pp. 101-108, Institute of Electrical and Electronics Engineers (IEEE) (2022) https://doi.org/10.1109/DSD57027.2022.00023
2019
Jose Nunez-Yanez, Energy Proportional Heterogenous Computing with Reconfigurable MPSoC, 2019 International Conference on High Performance Computing & Simulation (HPCS), 15-19 July (2019) https://doi.org/10.1109/HPCS48598.2019.9188229
Dave McEwan, Jose Nunez-Yanez, Relationship Estimation Metrics for Binary SoC Data, Proceedings of the Fifth International Conference on Machine Learning, Optimization, and Data Science, Italy, Lecture Notes in Computer Science 11943:118-129 (2019) https://doi.org/10.1007/978-3-030-37599-7_11
Dave McEwan, Marcin Hlond, Jose Nunez-Yanez, Visualizations for Understanding SoC Behaviour. Proceedings of 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), pp 277-280 (2019) https://doi.org/10.1109/PRIME.2019.8787837
Demetrios A. M. Coutinho, Kyriakos Georgiou, Kerstin I. Eder, Jose Nunez-Yanez, Samuel Xavier-de-Souza, Performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications, 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 06-09 October (2019) https://doi.org/10.1109/VLSI-SoC.2019.8920384
Mohammad Hosseinabady. Jose Nunez-Yanez, Heterogeneous FPGA+GPU Embedded Systems: Challenges and Opportunities, Proceedings of the Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES), pp 1-10 (2019) https://doi.org/10.48550/arXiv.1901.06331 
https://arxiv.org/abs/1901.06331
W. Beasley, B. Gatusch, D. Connolly-Taylor, C. Teng, A. Marzo and J. Nunez-Yanez, Ultrasonic Levitation with Software-Defined FPGAs and Electronically Phased Arrays, 2019 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Colchester, United Kingdom, pp. 41-48 (2019) https://doi.org/10.1109/AHS.2019.000-2
2018
J. Nunez-Yanez, M. Hosseinabady, A. Rodríguez, R. Asenjo, A. Navarro, R. Gran-Tejero, D. Suárez-Gracia, Simultaneous Multiprocessing on a FPGA+CPU Heterogeneous System-On-Chip, Parallel Computing is Everywhere. IOS Press BV, pp. 677-686 (2018) https://doi.org/10.3233/978-1-61499-843-3-677
Jose Nunez-Yanez, Mohammad Hosseinabady, Moslem Amiri, Andrés Rodríguez, Rafael Asenjo, Angeles Navarro, Rubén Gran-Tejero, Darío Suárez-Gracia, Parallelizing Workload Execution in Embedded and High-Performance Heterogeneous Systems, Proceedings of the Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES), HiPEAC, Manchester (2018) https://doi.org/10.48550/arXiv.1802.03316 https://arxiv.org/abs/1802.03316
M. Hosseinabady, J. L. Nunez-Yanez, Pipelined Streaming Computation of Histogram in FPGA OpenCL, Parallel Computing is Everywhere. IOS Press BV, pp. 632-641 (2018) https://doi.org/10.3233/978-1-61499-843-3-632
S. Amiri, M. Hosseinabady, S. McIntosh-Smith, J. Nunez-Yanez, Multi-precision convolutional neural networks on heterogeneous hardware, Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, pp. 419-424 (2018) https://doi.org/10.23919/DATE.2018.8342046
Sam Amiri, Mohammad Hosseinabady, Andres Rodriguez, Rafael Asenjo, Angeles Navarro and Jose Nunez-Yanez, Workload Partitioning Strategy for Improved Parallelism on FPGA-CPU Heterogeneous Chips, FPL18, Dublin, September (2018) https://doi.org/10.1109/FPL.2018.00071
2017
M. Hosseinabady, J. Nunez-Yanez, A Systematic Approach to Design and Optimise Streaming Applications on FPGA Using High-Level Synthesis, 27th International Conference on Field Programmable Logic and Applications (FPL), Ghent, Belgium (2017) https://doi.org/10.23919/FPL.2017.8056758
Q. Chen, V. Mishra, J. Nunez-Yanez, G. Zervas, Synchronizing reconfiguration of coherent functions on disaggregated FPGA resources, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-6 (2017) https://doi.org/10.1109/RECONFIG.2017.8279822.
Qianqiao Chen, Vaibhawa Mishra, Peter De Dobbelaere, Michael Enrico, Nick Parsons, Jose Nunez-Yanez, Georgios Zervas, SiP-Enabled FPGA Network Interface for Programmable Access to Disaggregated Data Centre Resources, 2017 Asia Communications and Photonics Conference (ACP), 0-13 November (2017) https://ieeexplore.ieee.org/document/8649413
Yhang Zhang, J. Nunez-Yanez, Optimal Compression of Vibration Data with Lifting Wavelet Transform and Context-based Arithmetic Coding, 25th European Signal Processing Conference (EUSIPCO), Khos, Greece (2017) https://doi.org/10.23919/EUSIPCO.2017.8081559
2016
J. Nunez-Yanez, Computing to the limit with heterogeneous CPU-FPGA devices in a video fusion application, In V. Bonato, C. Bouganis, & M. Gorgon (Eds.), Proceedings of Applied Reconfigurable Computing: 12th International Symposium, ARC 2016 Mangaratiba, RJ, Brazil, LNCS 9625:41-53 Springer Verlag (2016) https://doi.org/10.1007/978-3-319-30481-6_4
Awais Sani, J. Nunez-Yanez, Energy Proportional Computing with OpenCL on a FPGA-Based Overlay Architecture, In IEEE Nordic Circuits and Systems conference (NORCAS), Copenhagen, Denmark, November (2016) https://doi.org/10.1109/NORCHIP.2016.7792905
Mohd Zainol, J. Nunez-Yanez, CPCIe, A Compression-enabled PCIe Core for Energy and Performance Optimization, In IEEE Nordic Circuits and Systems conference (NORCAS), Copenhagen, Denmark, November (2016) https://doi.org/10.1109/NORCHIP.2016.7792892
Peng Sun, Alin Achim, Ian Hasler, Paul Hill, Jose Nunez-Yanez, Energy Efficient Video Fusion with Heterogenous CPU-FPGA devices, Design Automation and Test in Europe, Dresden, Germany (2016) https://ieeexplore.ieee.org/document/7459527
2015
K. Nikov, J. L. Nunez-Yanez, M. Horsnell, Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture, IEEE 13th International Conference on Embedded and Ubiquitous Computing (EUC), Porto, pp. 205-210 (2015) https://doi.org/10.1109/EUC.2015.32
M. Hosseinabady, J. L. Nunez-Yanez, Energy optimization of FPGA-based stream-oriented computing with power gating, 25th International Conference on Field Programmable Logic and Applications (FPL), London, pp. 1-6 (2015) https://doi.org/10.1109/FPL.2015.7293946
M. Hosseinabady, J. L. Nunez-Yanez, Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices, 25th International Conference on Field Programmable Logic and Applications (FPL), London, pp. 1-6 (2015) https://doi.org/10.1109/FPL.2015.7294016
2014
J. Nunez-Yanez, Arash Farhadi Beldachi, Run-time power and performance scaling with CPU-FPGA hybrids, NASA/ESA Adaptive Hardware and Systems conference, Leicester, UK, July (2014) https://doi.org/10.1109/AHS.2014.6880158
J. Nunez-Yanez, Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling, HEART (Highly Efficient Accelerators and Reconfigurable Technology), Sendai, Japan, June (2014) https://www.bristol.ac.uk/media-library/sites/engineering/research/migrated/documents/heart2014.pdf
Arash beldachi, Jose Luis Nunez-Yanez, Accurate Power control and monitoring in ZYNQ boards, Field Programmable Logic (FPL) 2014, Munich, September 2-4th (2014) https://doi.org/10.1109/FPL.2014.6927415
Jin chen, Jose Nunez-Yanez, Alin Achim, Joint Video Fusion and Super Resolution Based on Markov Random Fields, IEEE international conference on image processing (ICIP), Paris, October 27-30 (2014) https://doi.org/10.1109/ICIP.2014.7025431
Juan Carlos Moctezuma, Jose Luis Nunez-Yanez, Joseph P. McGeehan, Neuron Dynamics of Two-compartment Traub Model for Hardware-based Emulation, international conference on neural computation theory and applications 2014, Rome, 22-25 October (2014) https://doi.org/10.1016/j.micpro.2015.09.003
Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Run-Time Power Gating in Hybrid ARM-FPGA Devices, Field Programmable Logic (FPL) 2014, Munich, September 2-4th (2014) https://doi.org/10.1109/FPL.2014.6927503
Peng Sun, Jose Nunez-Yanez, Optimizing Memory Power in Hybrid ARM-FPGA Chips With Lossless Data Compression, FPGAWorld, Sweeden, September (2014) https://doi.org/10.1145/2674095.2674097
Y. Wu, J. Nunez-Yanez, R. Woods, D. Nikolopoulos, Power Modeling and Capping for Heterogeneous ARM/FPGA SoCs 2014 Proceedings of the 2014 International Conference on Field-Programmable Technology (FPT), IEEE Computer Society, p. 1 (2014) https://doi.org/10.1109/FPT.2014.7082782
2013
Jose Nunez-Yanez, Energy proportional computing in commercial FPGAs with adaptive voltage scaling, In Proceedings of the 10th FPGAworld Conference (FPGAworld ‘13). ACM, New York, NY, USA, Article 6, 5 pages (2013) https://doi.org/10.1145/2513683.2513689
J. C. Moctezuma, J. P. McGeehan, J. L. Nunez-Yanez, Numerically efficient and biophysically accurate neuroprocessing platform, 2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.1-6, 9-11 Dec. (2013) https://doi.org/10.1109/ReConFig.2013.6732313
Jin Chen, Jose Nunez-Yanez, Alin Achim, Video super-resolution using low rank matrix completion, IEEE international conference on image processing, ICIP13, Melbourne, Australia. pp. 1376-1380 (2013) https://doi.org/10.1109/ICIP.2013.6738283
2012
José L. Núñez-Yáñez, Arash Beldachi, Atukem Nabina, Mohammad Hosseinabady, Exploring dynamically reconfigurable multicore designs with NoRC designer. HPCS (High Performance Computing and Simulation) conference, 2012:pp. 254-260, June 3rd-5th. Madrid, Spain (2012) https://doi.org/10.1109/HPCSim.2012.6266921
Arash Farhadi Beldachi, Jose L. Nunez-Yanez, Reconfigurable router design and evaluation for the FPGA-friendly SoCWire network-on-chip. In Proceedings of the Annual FPGA Conference (FPGAworld ‘12). ACM, New York, NY, USA, Article 1, 6 pages (2012) https://doi.org/10.1145/2451636.2451637
Jin Chen, Jose Nunez-Yanez and Alin Achim, Approximate Alpha-stable Markov Random Fields for Video Super-resolution, 20th European Signal Processing Conference (EUSIPCO 2012), Bucharest, Romania, August 27-31 (2012) https://ieeexplore.ieee.org/document/6334091
2010
Atukem Nabina, Jose Nunez-Yanez, Dynamic Reconfiguration Optimisation with Streaming Data Decompression, FPL, pp.602-607, 2010 International Conference on Field Programmable Logic and Applications (2010) https://doi.org/10.1109/FPL.2010.118
Mohammad Hosseinabady, Jose L. Nunez-Yanez, Antonio Marcello Coppola, Task Dispersal Measurement in Dynamic Reconfigurable NoCs, ISLVLSI, pp.167-172, 2010 IEEE Computer Society Annual Symposium on VLSI (2010) https://doi.org/10.1109/ISVLSI.2010.91
Mohammad Hosseinabady, Jose Nunez-Yanez, Effective Modelling of Large NoCs using SystemC IEEE International Symposium on Circuits and Systems ISCAS10, pp. 161-164, Paris, May 30- June 2 (2010) https://doi.org/10.1109/ISCAS.2010.5538028
Mohammad Hosseinabady, Jose Nunez-Yanez, SystemC Architectural Transaction Level Modelling for Large NoCs, Forum on specification & Design Languages (FDL10), pp. 142-147, Southampton, UK, Sept 14-16 (2010) https://dblp.org/db/conf/fdl/fdl2010.html#HosseinabadyN10
2009
Jose Nunez-Yanez, Energy Optimization in a Network-On-Chip with Dynamically Reconfigurable Processing Nodes, Invited paper, 2009 IEEE Multi-conference on Systems and Control, Saint Petersburg, Russia, pp. 308-313, July 8-10 (2009) https://doi.org/10.1109/CCA.2009.5281128
Jose Nunez-Yanez, Trevor Spiteri, George Vafiadis, Fast Motion Estimation using Configurable and Extendable Processing Cores, IEEE 43rd Asilomar Conference on Signals, Systems and Computers, Monterey, CA, USA, November 1-4 (2009) https://doi.org/10.1109/ACSSC.2009.5469937
Mohammad Hosseinabady, Jose L. Nunez-Yanez, Run-Time Resource Management in Fault-Tolerant Network on Reconfigurable Chips, 19th International conference on Field Programmable Logic and Applications, pp. 574-577, Czech Republic, Prague, August 29-September 2 (2009) https://doi.org/10.1109/FPL.2009.5272400
T. Spiteri, G. Vafiadis, Jose Nunez-Yanez, Flexible motion estimation processors for high definition video coding, in Fifth UK Embedded Forum, Sep. 2009, eds. A. Koelmans, Michael J. Pont, ISBN 978-0-7017-0222-2, pp. 24-29 (2009) https://async.org.uk/ukef09/
Trevor Spiteri, George Vafiadis, Jose Luis Nunez-Yanez, A Toolset for the Analysis and Optimization of Motion Estimation Algorithms and Processors, 19th International conference on Field Programmable Logic and Applications, pp. 423-427, Czech Republic, Prague, August 29-September 2 (2009) https://doi.org/10.1109/FPL.2009.5272247
Wei Song, Doug Edwards, Jose Nunez-Yanez, Sohini Dasgupta, Adaptive stochastic routing in fault-tolerant on-chip networks, 3rd ACM/IEEE International Symposium on Networks-on-Chip NOCs, May 10-May 13 Pages 32-37, La Jolla, CA, USA (2009) https://doi.org/10.1109/NOCS.2009.5071442
Yiwei Zhang, José Nuñez-Yañez, Joe McGeehan, Edward Regan Stephen Kelly, A Biophysically Accurate Floating Point Somatic Neuroprocessor, 19th International conference on Field Programmable Logic and Applications, pp. 26-31, Czech Republic, Prague, August 29-September 2 (2009) https://doi.org/10.1109/FPL.2009.5272558
2008
J. L. Nunez-Yanez, E. Hung, V. Chouliaras, A configurable and programmable motion estimation processor for the H.264 video codec, International Conference on Field Programmable Logic and Applications, 2008, pp.149-154, 8-10 Sept (2008) https://doi.org/10.1109/FPL.2008.4629923
J. Nunez-Yanez, Eddie Hung, Xiaolin Chen, Nishan Canagarajah, A Configurable Pixel and Block Matching Motion Estimation Processor for Lossless and Lossy Video Compression, On-board Payload Data Compression Workshop, 26-27 June, Noordwijk, The Netherlands (2008)
Jose L. Nunez-Yanez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, Statistical Lossless Compression of Space Imagery and General Data in a Reconfigurable Architecture, (invited paper) 2008 NASA/ESA conference on Adaptive Hardware Systems, pp. 172-178, 22-25 June, Noordwijjk, Netherlands (2008) https://doi.org/10.1109/AHS.2008.9
I. Zaidi, A. Nabina, C. N. Canagarajah, J. Nunez-Yanez, Evaluating dynamic partial reconfiguration in the integer pipeline of a FPGA-based open-source processor, International Conference on Field Programmable Logic and Applications, 2008. FPL 2008. pp.547-550, 8-10 Sept (2008) https://doi.org/10.1109/FPL.2008.4630005
Izhar Zaidi, Atukem Nabina, C. N. Canagarajah, Jose Nunez-Yanez, Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration, Digital System Design Architectures, Methods and Tools, 2008. DSD ‘08. 11th EUROMICRO Conference on , vol., no., pp.592-598, 3-5 Sept. (2008) https://doi.org/10.1109/DSD.2008.92
Mohammad Hosseinabady, Jose Nunez-Yanez, Fault-tolerant dynamically reconfigurable NoC-based SoC, ASAP’08 19th IEEE International Conference Application-specific Systems, Architectures and Processors, Leuven, Belgium, June (2008) https://doi.org/10.1109/ASAP.2008.4580150
X. Chen, N. Canagarajah, J. L. Nunez-Yanez, Lossless Multi-mode Interband Image Compression and its Hardware Architecture, Conference on Design and Architectures for Signal and Image Processing (DASIP 2008), Brussels, Belgium, November (2008) https://doi.org/10.1007/978-90-481-9965-5_1
Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, Jose L. Nunez-Yanez, Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture, Applied Reconfigurable Computing Workshop (ARC), LNCS 4943, March, London, pp. 336-341 (2008) https://doi.org/10.1007/978-3-540-78610-8_38
2007
Jose L. Nunez-Yanez, Vassilios A. Chouliaras, Jiri Gaisler, Dynamic Voltage Scaling in a FPGA-based System-on-Chip, International conference on Field Programmable Logic and Applications 2007, Amsterdam, Netherlands, pp. 459-462, 27-29 August (2007) https://doi.org/10.1109/FPL.2007.4380689
Jose L. Nunez-Yanez, Xiaolin Chen, Nishan Canagarajah, Raffaele Vitulli, Dynamic Reconfigurable Hardware for Lossless Compression of Image, Video and General Data Content, (invited paper) XXII Conference on Design of Circuits and Integrated Systems, pp. 564-569, November, Sevilla, Spain (2007) ISBN-13 978-84690-8629-2
Robert Stapenhurst, Koushik Maharatna, Jimson Mathew, Jose Nunez-Yanez, On the Hardware Reduction of Z-Datapath of Vectoring CORDIC, IEEE International Symposium of Circuits and Systems (2007) https://doi.org/10.1109/ISCAS.2007.377978
V. A. Chouliaras, Jose Luis Nunez-Yanez, An IEEE 754 floating point engine designed with an electronic system level methodlogy, Norchip, 19-20 November (2007) https://doi.org/10.1109/NORCHP.2007.4481066
Xiaolin Chen, Nishan Canagarajah, Jose L. Nunez-Yanez, Hardware Architecture for Lossless Image Compression Based on Context-based Modeling and Arithmetic Coding, IEEE International SOC conference, September, Hsinchu Taiwan, pp. 251-254 (2007) https://doi.org/10.1109/SOCC.2007.4545469
2006
J. L. Nunez-Yanez, V. A. Chouliaras, D. Alfonso, F. Rovati, Hardware Assisted Rate Distortion Optimization with Embedded CABAC Accelerator for the H.264 Advanced Video Codec, 2006 Digest of Technical Papers International Conference on Consumer Electronics (ICCE), pp 95-96 (2006) https://doi.org/10.1109/ICCE.2006.1598327
K. Koutsomyti, V. Chouliaras, S. R. Parr, J. L. Nunez-Yanez, S. Datta, Accelerating Speech Coding Standards Through SystemC Synthesized SIMD and Scalar Accelerators, IEEE 2006 International Conference on Consumer Electronics (ICCE 2006), IEEE, Las Vegas USA, pp. 279-280, 10th January (2006) https://doi.org/10.1109/ICCE.2006.1598419
Xiaofeng Wu, Vassilios Chouliaras, J. L. Nunez-Yanez, Roger Goodall, Tanya Vladimirova, A Novel Processor Architecture for Real-Time Control, Proceedings of Asia-Pacific Conference on Advances in Computer Systems Architecture, Lecture Notes in Computer Science 4186:270-280 (2006) https://doi.org/10.1007/11859802_22
2005
J. L. Nunez-Yanez, V. A. Chouliaras, High-Performance Arithmetic Coding VLSI Macro for the H264 Video Compression Standard, 2005 Digest of Technical Papers, International Conference on Consumer Electronics (ICCE), pp 287-288 (2005) https://doi.org/10.1109/ICCE.2005.1429830
Jose L. Nunez-Yanez, Vassilios A. Chouliaras, Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec, 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP’05), pp. 411-416 (2005) https://doi.org/10.1109/ASAP.2005.30
Ashwin K. Kumaraswamy, V. A. Chouliaras, T. R. Jacobs, and J. L. Nunez-Yanez, System-on-Chip Design Framework (SDF) unifying Specification Capture and Design Modelling, accepted for publication at the 2005 Electronic Design Processes (EDP) Workshop (2005)
S. R. Parr, K. Koutsomyti, V. A. Chouliaras, J. L. Nunez-Yanez, D. J. Mulvaney, Configurable Scalar and Vector Coprocessors for Accelerating the G.723.1 and G.729A Speech Coders, IASTED International Conference on SIGNAL AND IMAGE PROCESSING, ACIT-SIP (2005) https://www.actapress.com/Abstract.aspx?paperId=20233 https://www.researchgate.net/publication/228995577_Configurable_scalar_and_vector_coprocessors_for_accelerating_the_G_7231_and_G_729A_speech_coders
Tom R. Jacobs, Vassilios A. Chouliaras, J.L Nunez-Yanez, A Thread and Data-Parallel MPEG4 Video Encoder for a System-On-Chip Multiprocessor, 16th IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP’05), pp. 405-410 (2005) https://doi.org/10.1109/ASAP.2005.11
V. A. Chouliaras, J. A. Flint, Li Yibin, J. L. Nunez-Yanez, A system-on-chip vector multiprocessor for transmission line modelling acceleration, IEEE Workshop on Signal Processing Systems Design and Implementation, pp. 568-572, 2-4 Nov (2005) https://doi.org/10.1109/SIPS.2005.1579931
Vassilios Chouliaras, J. L. Nunez-Yanez, Tom Jacobs, Ashwin K. Kumaraswamy, Configurable Multiprocessors for high-performance MPEG-4 video coding, to appear in IEEE Computer Society Annual Symposium on VLSI 2005, May 11-12 (2005) Tampa, Florida, USA https://doi.org/10.1109/ISVLSI.2005.24
2004
J. L. Nunez-Yanez, V. A. Chouliaras, Arithmetic Coding Hardware Acceleration in a SOPC Platform for Advanced Video Compression, International Conference on Reconfigurable Computing and FPGAs, ReConFig04, Colima, Mexico, 2004. Best paper award ReconFIG (2004)
K. Koutsomyti, S. R. Parr, V. A. Chouliaras, J. L. Nunez-Yanez, D. J. Mulvaney, S. Datta, Scalar and Parametric Vector Accelerators for the G.729A Speech Coding Standard, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Loughborough University, Sept (2004)
N. G. Bartzoudis, A. G. Fragkiadakis, D. J. Parish, J. L. Nunez-Yanez, A System for Fault Detection and Reconfiguration of Hardware Based Active Networks, 10th IEEE International On-Line Testing Symposium, Funchal, Madeira Island, Portugal (2004) https://doi.org/10.1109/OLT.2004.1319689
T. R. Jacobs, V. A. Chouliaras, D. J. Mulvaney, J. L. Nunez-Yanez, The Application of Thread-Level Parallelism for Reducing the Architectural Complexity of an MPEG2 Encoder, IEE/ACM SoC Design, Test and Technology Postgraduate Seminar, Loughborough University, Sept (2004)
V. A. Chouliaras, J. L. Nunez-Yanez, S. Agha, Silicon Implementation of Parametric Vector Datapath for Real-Time MPEG2 Encoding, The sixth IASTED International Conference on Signal & Image Processing, pp. 298-304, Honolulu, Hawaii (2004) https://www.actapress.com/Abstract.aspx?paperId=18099
2003
E. G. Nikolova, D. J. Mulvaney, V. A. Chouliaras, J. L. Nunez-Yanez, A Novel Code Compression/Decompression Approach for High-performance SoC Design, IEE Seminar on SoC Design, Test and Technology, Cardiff University, Cardiff, UK, 2 September (2003)
E. G. Nikolova, D. J. Mulvaney, V. A. Chouliaras, J. L. Nunez-Yanez, A novel code compression decompression approach to high performance SoC design, International Symposium on System-On-Chip design, Tampere, Finland, Nov 19-21 (2003)
M. Milward, J. L. Nunez-Yanez, D. Mulvaney, Routing Strategies for High-Speed Parallel Data Compression, PDPTA 2003:Las Vegas, Nevada, USA – Volume 2, pp. 635-641 (2003)
N. G. Bartzoudis, A. G. Fragkiadakis, D. J. Parish, J. L. Nunez-Yanez, A Monitor Module for Active Networks with Hardware Support, IEE Seminar on SoC Design, Test and Technology, Cardiff University, Cardiff, UK, 2 September (2003)
N. G. Bartzoudis, A. G. Fragkiadakis, D. J. Parish, J. L. Nunez-Yanez, M. J. Sandford, Reconfigurable Computing and Active Networks, in Proceedings of The 2003 International Multiconference in Computer Science & Engineering (ERSA’03), Las Vegas, U.S.A., June (2003) pp. 280-284
2002
J. L. Nunez-Yanez and S. Jones, Lossless Data Compression Programmable Hardware for High-Speed Data Networks, Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), Hong Kong, China, pp. 290-293, December (2002)
2001
J. L. Nunez-Yanez, C. Feregrino, S. Jones, S. Bateman, X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor, pp. 613, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29 (2001)
J. L. Nunez-Yanez, S. Jones, S. Bateman, X-MatchPRO: A high performance full-duplex lossless data compressor on a ProASIC FPGA, Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications IDAACS’2001 (2001)
R. Stefo, J. L. Nunez-Yanez, C. Feregrino, S. Mahapatra, S. Jones, FPGA-based modelling unit for high speed lossless arithmetic coding, 11th International Conference on Field Programmable Logic and Applications FPL’2001, Belfast, Northern Ireland, UK, August 27-29 (2001)
2000
J. L. Nunez-Yanez, S. Jones, The X-MatchPRO 100 Mbytes/second FPGA-Based Lossless Data Compressor, Proceedings of Design, Automation and Test in Europe, DATE Conference 2000, pp.139-142, March (2000) https://doi.org/10.1109/IDAACS.2001.941979
1999
J. L. Nunez-Yanez, C. Feregrino, S. Bateman, S. Jones, The X-MatchLITE FPGA-Based Data Compressor, Proceedings of the 25th EUROMICRO Conference, Digital Systems Design: Architectures, Methods and Tools, pp. 126-132, September (1999) https://doi.org/10.1109/EURMIC.1999.794458
J. M. Moreno, J. L. Nunez-Yanez, J. Madrenas, J. Cabestany, J. R. Laúna. VLSI Implementation of a Neural Decision Engine for Commercial Coin Recognizers. Electron technology, 32:266-271 (1999)